1. Field of the Invention
Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. Other example embodiments of the present invention relate to an electrode structure having increased characteristics, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device.
2. Description of the Related Art
There are several types of semiconductor memory devices (e.g., static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, flash memory devices or the like). The semiconductor devices may be divided into two classes, volatile memory devices and non-volatile memory devices, depending on whether data is retained when the power supply is turned off or deactivated. Among the non-volatile memory devices, flash memory devices may be used in electronic devices (e.g., a digital camera, a cellular phone, and a MP3 player) for maintaining data. Flash memory devices may require a longer amount of time for reading or writing data such that alternative memory devices may be necessary. For example, the alternative memory devices may include ferroelectric RAM (FRAM) devices, magnetic RAM (MRAM) devices, phase-change RAM (PRAM) devices or the like.
The phase-change memory devices may include a phase-change material layer. A crystalline structure of the phase-change material layer may vary in accordance with an amount of heat generated by a current applied to the phase-change material layer, The phase-change material layer used in the phase-change memory devices may include chalcogenide (e.g., germanium-antimony-tellurium (Ge—Sb—Te) (also known as GST)). The crystalline structure of the phase-change material layer may vary according to a time duration and the mount of heat generated by the current applied thereto.
Amorphous phase-change material may have a relatively higher specific resistance, and crystalline phase-change material may have a relatively lower specific resistance. Phase-change memory devices may be altered to store data therein by utilizing various resistances of different phase-change materials. In order to maintain more uniformly resistance characteristics, an electrode of the phase-change memory device may have a smaller cross section and a more uniform surface.
Conventional methods of manufacturing a phase-change memory device have been acknowledged.
FIGS. 1A to 1D are diagrams illustrating cross sectional views of a conventional method of manufacturing a phase-change memory device.
Referring to FIG. 1A, a first insulating interlayer 10 may be formed on a substrate (not shown) using an oxide. The substrate may include a transistor having a gate structure and source/drain regions. A first pad 15 may be formed through the first insulating interlayer 10. The first pad 15 may include a conductive material and may contact the source/drain region of the transistor.
A second insulating interlayer 20 may be formed on the first pad 15 and the first insulating interlayer 20 using an oxide. A second pad 25 that contacts the first pad 14 may be formed through the second insulating interlayer 20.
A silicon oxynitride layer 30 and a silicon oxide layer 35 may be sequentially formed on the second pad 25 and the second insulating interlayer 20.
Referring to FIG. 1B, the silicon oxynitride layer 30 and the silicon oxide layer 35 may be partially etched by a lithography process, forming a silicon oxynitride layer pattern 32 and a silicon oxide layer pattern 37. The silicon oxynitride layer pattern 32 and the silicon oxide layer pattern 37, collectively, may have an opening 40 exposing the second pad 25. A conductive layer 45 may be formed on the silicon oxide layer pattern 37 to cover the opening 40.
Referring to FIG. 1C, the conductive layer 45 may be partially removed by a chemical mechanical polishing (CMP) process until the silicon oxide layer pattern 37 is exposed, forming a conductive layer pattern within the opening 40.
The silicon oxide layer pattern 37 may be removed by an etch-back process to expose the silicon oxynitride layer pattern 32. The conductive layer pattern may protrude from an upper surface of the silicon oxynitride layer pattern 32 in a pillar shape.
An upper portion of the protruded the conductive layer pattern may be removed by a CMP process to form a lower electrode 50 within the silicon oxynitride layer pattern 32.
Referring to FIG. 1D, a phase-change layer pattern 55 and an upper electrode 60 may be sequentially formed on the lower electrode 50 and the silicon oxynitride layer pattern 32.
A third insulating interlayer 65 may be formed using an oxide to cover the upper electrode 60. A fourth insulating interlayer 68 may be formed on the third insulating interlayer 65 and the upper electrode 60.
The fourth insulating interlayer 68 may be partially etched to expose the upper electrode 60. An upper contact 70 may be formed on the upper electrode 60. An upper wiring 75 may be formed on the upper contact 70 and the fourth insulating interlayer 68, forming a phase-change memory device.
According the conventional method, the conductive layer pattern and the silicon oxynitride layer pattern 32 may have a relatively lower etching selectivity in the CMP process using metal slurry for forming the lower electrode 50. The silicon oxynitride layer pattern 32 may be etched more than the conductive layer. Alternatively, the conductive layer may be etched more than the silicon oxynitride layer pattern 32. The silicon oxynitride layer pattern 32 may be etched simultaneously with the conductive layer in a formation of the lower electrode 50. After forming the lower electrode 50, a thickness of the silicon oxynitride layer pattern 32 may not be uniform and roughness of the lower electrode 50 may increase. As an initial thickness of the lower electrode 50 and the silicon oxynitride layer pattern 32 may be increased, forming the phase-change layer pattern 55 on the lower electrode 50 and the silicon oxynitride layer pattern 32 may be more difficult. As a surface of the lower electrode 50 becomes rougher, electric characteristics of the lower electrode 50 may be deteriorate such that properties of the phase-change memory device including the lower electrode 50 may deteriorate.